Write all code in Verilog or System Verilog so that it would…
Write all code in Verilog or System Verilog so that it would compile, simulate, and synthesize without errors or warnings, for full credit indent blocks and organize your code clearly. All variables must be declared. If you use System Verilog clearly state you are using it for credit. Your code should be efficient, succinct (about the minimum number of lines). Use the Boolean expression from the previous problem. Organize your work and answer carefully. Disorganized solutions and responses will be penalized. a) Write a Verilog or System Verilog module named Funb that evaluates F using a Boolean expression. To get credit this should be done using a Behavioral model in the form of a Boolean expression in Verilog. Use the original, unsimplified of the expression. Inputs are A, B and C. Output is F. b) Is this statement True or false (only one answer) — The structural model causes the synthesizer to build the logic exactly as described, whereas the behavioral model builds the simplest structure that has that behavior. Your answer to b) should be simply True or False.