_____ provides 80–90% of the body’s vitamin D stores?

 Leucovorin rescue should be provided with which of the following chemotherapy agents?

  If infused directly into an IV line or not sufficiently diluted when mixed with phosphate, which of the following will precipitate?

Problem 3: Adder Design (16 pts) Consider a 24-bit adder design based on the Carry-Bypass architecture. PG is the logic unit to produce P and G. Assume the following delays for each 1-bit adder: tPG (delay to produce Pi and Gi signals from Ai and Bi) = 4 tcarry (delay to compute Cout,i from Pi, Gi and Cin,i) = 1 tsum (delay to compute Sumi from Pi, Gi and Cin,i) = 4 tmux (delay for the multiplexor) = 2 The registers are identical flip-flops (FFs) that are triggered by the rising edge of the clock: tC2Q (clock-to-Q delay of a one-bit FF) = 2 tsu (setup time of a one-bit FF) = 1 thold (hold time of a one-bit FF) = 1 For the entire problem, assume these delays are independent of the fan-in.    A. This 24-bit Carry-Bypass adder has 6 stages. Assume each stage has 4 bits. What is the minimum clock period in this 24-bit adder design? (4 pts)  (Hint: the first group carry propagates 3 bits after setup delay)   B. Starting from Bit-8, as highlighted in the figure above, what is the delay of the longest logic path? You don’t need to include input and output FFs. (3 pts) Delay =                             C. There are many non-critical paths in the design of Part A, such as the path starting from Bit-4 or from Bit-8. We plan to improve the design by making these non-critical paths slower. The figure below presents a new design, in which the number of bits in each stage is now equal: 2, 4, 6, 6, 4, 2. What is the minimum clock period in this new design? (4 pts)   D. What is the delay of the longest logic path from Bit-6 to Bit-21, as highlighted in the figure? You don’t need to include input and output FFs. (3 pts) Delay =                              E. What is the primary advantage of this new design, as compared to the design in Part A? (2 pts) Advantage =                             

1.5 The right figure shows the clock tree for a 16 core design. Each solid square represents a core. All cores are identical. The inverters in the clock tree have the same size. Each inverter has a nominal delay of 100ps and a random variation of ±20ps. The wire segments in the clock tree are symmetric with respect to RC delay. 1.5.1 What is the maximum clock skew of this clock tree? (1 pts) 1.5.2 What is the maximum clock jitter of this clock tree? (1 pts)

1.7 The figure above presents the design of a sequential machine. The registers are all flip-flops, triggered by the rising edge of the clock. They have tC2Q = 1, tsu = 1, and thold = 1. All four logic blocks are identical, with the logic delay tL = 3. The delay through the multiplexer tM = 2. (A)

1.2 When CMOS technology is scaling down from 28nm to 7nm, which of the following statements is TRUE for on-chip interconnect? You may select more than one. (2 pts) The pitch of metal-1 stays the same. RC delay of metal wires becomes less important as compared to standard cell delay. Crosstalk noise becomes more severe at 7nm. Fewer buffers are inserted to the global interconnect.

1.2  A read-only memory (ROM) with 9 cells is shown in the figure. All NMOS transistors have the same size and all PMOS transistors have the same size. 1.2.1 Is this a NOR-based ROM or NAND-based ROM? Please write the answer. (1 pts)   1.2.2 Please identify which cell has the fastest read speed and which cell has the longest read delay, in the format of (WL, BL).  (4 pts).    1.2.3 Due to the leakage at the standby mode, the voltage at BLs does not reach full VDD. Which solution below will be able to restore the BL voltage to VDD at the standby mode? (1 pts)    a. Reduce the size of the PMOS transistor    b. Reduce the threshold voltage of the NMOS transistor    c. Reduce the supply voltage VDD    d. Add a keeper at the output of BLs

1.6 Consider the multiplication of two 9-bit numbers A and B, with A = 101101101. Using the booth encoding algorithm, which B value will result in the largest number of partial products? (2 pts) a. 101010101 b. 111111111 c. 100011111 d. 111110101    

1.5 To check possible setup time violations, which of the following conditions should be used in SPICE for logic path delay? (2 pts) Fast NMOS and fast PMOS, low VDD and high temperature Fast NMOS and fast PMOS, high VDD and low temperature Slow NMOS and slow PMOS, low VDD and high temperature Slow NMOS and slow PMOS, high VDD and low temperature