Parallel_Systems_3 Shared Memory Machines 3. [2 points] Cons…

Parallel_Systems_3 Shared Memory Machines 3. Consider a shared address space architecture.  The address space is divided into two partitions:  Partition A is NCC-NUMA  Partition B is CC-NUMA  What guarantees are needed from the architecture to ensure that it provides sequential consistency memory model to the programmer? 

Parallel_Systems_4b M.E.Lock The context for this question i…

Parallel_Systems_4b M.E.Lock The context for this question is the same as the previous question. 4. Consider the following lock algorithm: while ((L == locked) or (T&S(L) == locked)) {    while (L == locked); // spin    delay (d); // different delays for different processors  }  // success if we are here    b. What are the program characteristics that would negatively impact the program’s performance with this lock algorithm implementation? In what way does it reduce performance? 

Parallel_Systems_5b M.E.Lock The context for this question i…

Parallel_Systems_5b M.E.Lock The context for this question is the same as the previous question. 5. Consider the ticket lock algorithm from lecture 4 (slide 108): b. What are the downsides of the ticket lock algorithm for systems with write-update cache coherence? Briefly explain your answer.