A timing diagram is given for inputs to a D Flip-Flop with E…

A timing diagram is given for inputs to a D Flip-Flop with Enable and Reset (both active high, reset is synchronous). What is the value of the Q output of the D Flip-Flop with Enable and Reset at time = 5 ns? Assume the delay from inputs changing to output changing is negligible.

A timing diagram is given for inputs to a D Flip-Flop with E…

A timing diagram is given for inputs to a D Flip-Flop with Enable and Reset (both active high, reset is synchronous). What is the value of the Q output of the D Flip-Flop with Enable and Reset at time = 13 ns? Assume the delay from inputs changing to output changing is negligible.

A truth table with four output functions is given. Function…

A truth table with four output functions is given. Function Y2 will be implemented using a 4:16 decoder that has address inputs A3:0 and outputs Y0, Y1, …, Y15.  Which outputs need to be connected to an OR gate to produce function Y2 (do not confuse function Y2 with output Y2 on the decoder)?