How many D flip-flops are needed to represent 6 different states?

A timing diagram is given for inputs to a D Flip-Flop with Enable and Reset (both active high, reset is synchronous). What is the value of the Q output of the D Flip-Flop with Enable and Reset at time = 5 ns? Assume the delay from inputs changing to output changing is negligible.

A timing diagram is given for inputs to a basic D Flip-Flop. What is the value of the Q output of the D Flip-Flop at time = 5 ns? Assume the delay from inputs changing to output changing is negligible.

A timing diagram is given for inputs to a D Flip-Flop with Enable and Reset (both active high, reset is synchronous). What is the value of the Q output of the D Flip-Flop with Enable and Reset at time = 13 ns? Assume the delay from inputs changing to output changing is negligible.

A truth table with four output functions is given. Function Y2 will be implemented using a 4:16 decoder that has address inputs A3:0 and outputs Y0, Y1, …, Y15.  Which outputs need to be connected to an OR gate to produce function Y2 (do not confuse function Y2 with output Y2 on the decoder)? 

Convert 7010 to an 8-bit two’s complement number (ex: “01101110”)

Given: F(A,B,C).  Which of the following is the minterm of F that corresponds to A=0, B=0, C=1?

Given the following circuit: What function is implemented by Y2?

Given: A basic 3:8 decoder has address inputs A2:0 and outputs Y0, Y1, …, Y7. Suppose A2 = 1, A1 = 0 and A0 = 0.  Select the correct answer.

Given: F(A,B,C).  Which of the following is the minterm of F that corresponds to A=0, B=1, C=0?