How many D flip-flops are needed to represent 11 different states?

A timing diagram is given for inputs to a D Flip-Flop with Enable and Reset (both active high, reset is synchronous). What is the value of the Q output of the D Flip-Flop with Enable and Reset at time = 13 ns? Assume the delay from inputs changing to output changing is negligible.

Given: 101101002  is an 8-bit two’s complement number. What is its value in decimal (ex: “-25”, “45”)

A truth table with four output functions is given. Function Y3 will be implemented using a 4:16 decoder that has address inputs A3:0 and outputs Y0, Y1, …, Y15.  Which outputs need to be connected to an OR gate to produce function Y3 (do not confuse function Y3 with output Y3 on the decoder)? 

Given:  Which of the following describes the same function?

Given: A basic 3:8 decoder has address inputs A2:0 and outputs Y0, Y1, …, Y7. Suppose A2 = 0, A1 = 1 and A0 = 1.  Select the correct answer.

A truth table with four output functions is given. Function Y3 will be implemented using a 4:16 decoder that has address inputs A3:0 and outputs Y0, Y1, …, Y15.  Which outputs need to be connected to an OR gate to produce function Y3 (do not confuse function Y3 with output Y3 on the decoder)? 

A timing diagram is given for inputs to a D Flip-Flop with Enable and Reset (both active high, reset is synchronous). What is the value of the Q output of the D Flip-Flop with Enable and Reset at time = 9 ns? Assume the delay from inputs changing to output changing is negligible.

Given: F(A,B,C).  Which of the following is the minterm of F that corresponds to A=0, B=0, C=1?

A timing diagram is given for inputs to a D Flip-Flop with Reset (synchronous, active high). What is the value of the Q output of the D Flip-Flop with Reset at time = 13 ns? Assume the delay from inputs changing to output changing is negligible.