A timing diagram is given for inputs to a D Flip-Flop with Reset (synchronous, active high). What is the value of the Q output of the D Flip-Flop with Reset at time = 13 ns? Assume the delay from inputs changing to output changing is negligible.

Given: If you were to put this function into the K-map below, what value would go into the square marked S24?

A timing diagram is given for inputs to a D Flip-Flop with Enable (active high). What is the value of the Q output of the D Flip-Flop with Enable at time = 15 ns? Assume the delay from inputs changing to output changing is negligible.

Suppose the switching frequency in a digital circuit is cut in half (the frequency is now half what it was before). If nothing else changed, how does that affect the power consumption?

Given: If you were to put this function into the K-map below, what value would go into the square marked S24?

Given: F(A,B,C).  Which of the following is the minterm of F that corresponds to A=1, B=0, C=0?

A timing diagram is given for inputs to a D Flip-Flop with Enable (active high). What is the value of the Q output of the D Flip-Flop with Enable at time = 15 ns? Assume the delay from inputs changing to output changing is negligible.

Given: A basic 3:8 decoder has address inputs A2:0 and outputs Y0, Y1, …, Y7. Suppose A2 = 0, A1 = 1 and A0 = 1.  Select the correct answer.

A timing diagram is given for inputs to a D Flip-Flop with Reset (synchronous, active high). What is the value of the Q output of the D Flip-Flop with Reset at time = 15 ns? Assume the delay from inputs changing to output changing is negligible.

A truth table with four output functions is given. Function Y1 will be implemented using a 4:16 decoder that has address inputs A3:0 and outputs Y0, Y1, …, Y15.  Which outputs need to be connected to an OR gate to produce function Y1 (do not confuse function Y1 with output Y1 on the decoder)?