Convert 9710 to an 8-bit two’s complement number (ex: “01101110”)

Given:  Which of the following describes the same function?

Given: An 8:1 multiplexer has data inputs D0, D1, …, D7, select inputs S2:0, and output Y. Suppose D0 = 1, D1 = 0, D2 = 0, D3 = 0, D4 = 1, D5 = 0, D6 = 1, D7 = 1, S2 = 1, S1 = 1, and S0 = 0.  What is the value of Y?

A timing diagram is given for inputs to a D Flip-Flop with Enable (active high). What is the value of the Q output of the D Flip-Flop with Enable at time = 13 ns? Assume the delay from inputs changing to output changing is negligible.

Suppose the switching frequency in a digital circuit is doubled (the frequency is now twice what it was before). If nothing else changed, how does that affect the power consumption?

How many D flip-flops are needed to represent 23 different states?

Given: A basic 3:8 decoder has address inputs A2:0 and outputs Y0, Y1, …, Y7. Suppose A2 = 1, A1 = 1 and A0 = 0.  Select the correct answer.

Given: An 8:1 multiplexer has data inputs D0, D1, …, D7, select inputs S2:0, and output Y. Suppose D0 = 1, D1 = 0, D2 = 0, D3 = 0, D4 = 1, D5 = 0, D6 = 1, D7 = 1, S2 = 0, S1 = 0, and S0 = 1.  What is the value of Y?

A timing diagram is given for inputs to a D Flip-Flop with Reset (synchronous, active high). What is the value of the Q output of the D Flip-Flop with Reset at time = 1 ns? Assume the delay from inputs changing to output changing is negligible.

A timing diagram is given for inputs to a D Flip-Flop with Enable and Reset (both active high, reset is synchronous). What is the value of the Q output of the D Flip-Flop with Enable and Reset at time = 9 ns? Assume the delay from inputs changing to output changing is negligible.