Consider a page-fault that occurs in a 5-stage pipeline duri…

Consider a page-fault that occurs in a 5-stage pipeline during MEM, what should be the order of the tasks below to allow for the hardware to re-start the instructions? Please use a single space to separate the options (e.g. 1 2 3 4) with no leading or trailing whitespaces. Points may be deducted for misformatted responses. Options: Service the page fault Persist changes to the register file (allow the instruction already in WB to complete) Replace the instructions in IF, ID, EX with NOPs, and start sending NOPs from IF Resume the pipeline from the faulting instruction

Consider that we have two setups for hierarchical memory wit…

Consider that we have two setups for hierarchical memory with the following miss rates and hit times: Memory 1   Memory 2 Hardware Miss Rate Hit Time   Hardware Miss Rate Hit Time L1 Cache 0.07 8ns   L1 Cache 0.1 3ns L2 Cache 0.22 12ns   L2 Cache 0.38 10ns L3 Cache 0.31 30ns   L3 Cache 0.4 19ns Main Memory 0 70ns   Main Memory 0 56ns Compute the AAT (average access time) for each setup. Show your work in the textbox below to receive partial credits.