Suppose the switching frequency in a digital circuit is doubled (the frequency is now twice what it was before). If nothing else changed, how does that affect the power consumption?

A timing diagram is given for inputs to a basic D Flip-Flop. What is the value of the Q output of the D Flip-Flop at time = 13 ns? Assume the delay from inputs changing to output changing is negligible.

Q3- A 8 points Let ​A​ = {2, 5, 8} and let ​R​ be the relation with digraph with vertex set V and edge set E. Set of Vertices V = {2, 5, 8} Set of Edges E = {(2,2), (5,5), (8,8), (2,5), (2,8), (5,8)}. Note: (2,2) means a loop from the vertex 2 to itself, (2,8) means an edge from vertex 2 to 8, etc, . . .  Test this relation for the following properties: reflexive symmetric transitive

True of False: A sequential circuit has state.

Given: 01000001010010000000000000000000 is an IEEE-754 single precision floating-point number.  What are the first 6 bits of the mantissa (ex: “0.00000”)?

Given the following circuit: If the inputs are E=1, A=1 and B=1, what is the value of Y?

A truth table with four output functions is given. Function Y1 will be implemented using a 4:16 decoder that has address inputs A3:0 and outputs Y0, Y1, …, Y15.  Which outputs need to be connected to an OR gate to produce function Y1 (do not confuse function Y1 with output Y1 on the decoder)? 

A timing diagram is given for inputs to a D Flip-Flop with Reset (synchronous, active high). What is the value of the Q output of the D Flip-Flop with Reset at time = 5 ns? Assume the delay from inputs changing to output changing is negligible.

Given: 101101002  is an 8-bit two’s complement number. What is its value in decimal (ex: “-25”, “45”)

Given: A basic 3:8 decoder has address inputs A2:0 and outputs Y0, Y1, …, Y7. Suppose A2 = 0, A1 = 0 and A0 = 1.  Select the correct answer.