A truth table with four output functions is given. Function Y3 will be implemented using a 4:16 decoder that has address inputs A3:0 and outputs Y0, Y1, …, Y15.  Which outputs need to be connected to an OR gate to produce function Y3 (do not confuse function Y3 with output Y3 on the decoder)? 

A timing diagram is given for a 3-bit counter. What is the value of the Q0 output at time = 55 ns?  Assume the delay from inputs changing to outputs changing is negligible.

A timing diagram is given for inputs to a D Flip-Flop with Enable and Reset (both active high, reset is synchronous). What is the value of the Q output of the D Flip-Flop with Enable and Reset at time = 9 ns? Assume the delay from inputs changing to output changing is negligible.

Given: A basic 3:8 decoder has address inputs A2:0 and outputs Y0, Y1, …, Y7. Suppose A2 = 1, A1 = 0 and A0 = 0.  Select the correct answer.

Convert 20110 to an 8-bit unsigned binary number (ex: “01101110”)

Given: F(A,B,C).  Which of the following is the minterm of F that corresponds to A=1, B=0, C=0?

Given:  The size of a memory array is 1024 x 8.  How many bits does the RD line have?

Given: A finite state machine has 14 states.  What is the minimum number of flip-flops required if binary encoding is used to encode the state?

True or False: Integer multipliers are generally slower than floating-point multipliers

Given: A finite state machine has 8 states. What is the minimum number of flip-flops required if one-hot encoding is used to encode the state?