A standard soccer field covers an area of 7140 m2. Given tha…

A standard soccer field covers an area of 7140 m2. Given that there are 39.37 inches in a meter and exactly 12 inches in a foot, calculate the area of a soccer field in square feet. A) 663 ft2 B) 2.34×104 ft2 C) 7.69×104 ft2 D) 3.37×106 ft2 E) 1.11×107 ft2

A certain element has two naturally occurring isotopes, 10Jo…

A certain element has two naturally occurring isotopes, 10Jo and 11Jo (do not look for this element on the Periodic Table, it does not exist). The average atomic mass for this element is 10.811 amu. The natural abundance of 10Jo is 19.9% and its mass is 10.0129 amu. Calculate the mass of 11Jo. A) 10.0129 amu B) 11.0093 amu C) 80.1000 amu D) 10.8110 amu E) 10.4112 amu

12.9 grams of Reactant A (Molar Mass = 115.328 g/mol) reacts…

12.9 grams of Reactant A (Molar Mass = 115.328 g/mol) reacts with excess Reactant B producing 10.4 grams of Product C (Molar Mass = 154.765 g/mol) according to the reaction below: 2 A + B → 4 C + 3 D What is the percent yield of this reaction? A) 86.6 % B) 100 % C) 67.2 % D) 30.0 % E) 44.9 %

Fill in the following VHDL so that it will synthesize to the…

Fill in the following VHDL so that it will synthesize to the exact circuit shown. Note that every register has a clock and reset signal that is not shown. Breakup your answer into the different regions shown by preceding your code for each region with the corresponding region name. Use the “pre-formatted” style to make it easier to grade the code library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity example is generic ( width : positive := 16); port ( clk : in std_logic; rst : in std_logic; in1, in2, in3, in4 : in std_logic_vector(width-1 downto 0); out1, out2 : out std_logic_vector(width-1 downto 0));end example;architecture BHV of example is// REGION 1begin process(clk, rst) begin if (rst = ‘1’) then // REGION 2 elsif (clk’event and clk = ‘1’) then // REGION 3 end if; end process; // REGION 4end BHV;

Assume you have a pipelined datapath for the following loop….

Assume you have a pipelined datapath for the following loop.  Assume separate input and output memories, each with bandwidths of 256 bits per cycle. Assume you are using an FPGA with 32 multipliers. How many iterations of the loop can be performed in parallel? Assume an unsigned short is 16 bits. unsigned short a, b;for (int i=0; i < 1000000; i++) { a = b*10 + b*20 + b*30 + b*40;}