Assume the following information for a *single* level paging…

Assume the following information for a *single* level paging virtual address translation. The page size for a virtual memory system is 4KB The frame size for a physical memory is 4KB The Translation Look-aside Buffer (TLB) is direct-mapped with 8 sets and each set contains one translation. The number of bits in a virtual address is 32 The number of bits in a physical address is 28 Each question below worths 2 point. What is the number of virtual pages? What is the number of physical pages (frames)? How many bits are used in the virtual address for the page/frame offset? How many bits are used in the virtual address for the TLB index? How many bits are used in the virtual address for the TLB tag? What is the page number of the virtual address 0xCD1E9AC? What is the TLB index value and TLB tag value of the virtual address 0xCD1E9AC?

Consider the following truth table for 3 logic operations NO…

Consider the following truth table for 3 logic operations NO, NAND, and XOR  on single bit a and b.     Also consider the following 1-bit ALU that performs AND, OR, and addition on a and b.                           Note that one can select between three values using the Operation select line to the Result multiplexor. Assume that the Ainvert and Binvert signals can be asserted or de-asserted and that the CarryIn signal can be de-asserted or taken from the CarryOut of the preceding 1-bit ALU.  Pick a set of control signals for each Boolean logic operator. Some will go unused.

In order to design a circuit that takes three bits (x2, x1,…

In order to design a circuit that takes three bits (x2, x1, x0) as input and produces one output bit (0), the following K-map truth table is built to produce 1 as an output (0) if and only if x2x1x0 representing a 3-bit two’s complement is positive. Select the most simplified sum-of-product form for the output (0).