A digital computer has a memory unit with 32 bits per word….

A digital computer has a memory unit with 32 bits per word. The instruction set consists of 110 different operations. All instructions have an operation code part (opcode) and two address fields: one for a memory address and one for a register address. This particular system includes eight general-purpose, user-addressable registers. Registers may be loaded directly from memory, and memory may be updated directly from the registers. Direct memory-to-memory data movement operations are not supported. Each instruction is stored in one word of memory.   (a)The number of bits needed for the opcode parts . mandatory  (b)The number of bits needed to specify the register address extra credit (c)The number bits are left for the memory address part of the instruction. extra credit (d) Based on the number of bits needed for memory addressing that you have found in (c) what is the maximum allowable size for memory in the above architecture i.e. how many unique memory locations can be addressed with that many bits. extra credit For extra credits, you get either full credit or 0 if it is correct or incorrect. No part credit will be given for attempting. The score will be added as fudge points.

Fill in the following parts. Recall that AMAT = Hit Time + M…

Fill in the following parts. Recall that AMAT = Hit Time + Miss Rate * Miss Penalty (a)  Assume Hit Time is 1 cycle and the miss penalty is 100 cycles. What should be the value of the miss rate to achieve an AMAT of 2 cycles?    (b) As in (a.) but now assume the miss penalty is 800 cycles. What is the miss rate needed to achieve an AMAT of 2 cycles?    (c)  Assume a two-level cache where the L1 hit time is as in (a.) and the hit time in the L2 cache is 2 cycles and the miss penalty is 800 cycles. Further, assume an L1 miss rate of 0.1. Show how you calculate the L2 miss rate to achieve an AMAT of 2 cycles. What is the L2 miss rate you calculated?