1.5 The right figure shows the clock tree for a 16 core desi…
1.5 The right figure shows the clock tree for a 16 core design. Each solid square represents a core. All cores are identical. The inverters in the clock tree have the same size. Each inverter has a nominal delay of 100ps and a random variation of ±20ps. The wire segments in the clock tree are symmetric with respect to RC delay. 1.5.1 What is the maximum clock skew of this clock tree? (1 pts) 1.5.2 What is the maximum clock jitter of this clock tree? (1 pts)