Fill in the VHDL to implement the illustrated circuit. Assum…
Fill in the VHDL to implement the illustrated circuit. Assume that clk and rst connect to every register in the schematic. All wires/operations are width bits except for in4, which is a single bit. Ignore adder overflow. Assume the mux selects the left input when in4 = ‘1’. Use the next page if necessary. — Write code in specified regions creating the diagram used above –library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity diagram is generic (width : positive := 8); port( clk, rst : in std_logic; in1, in2, in3 : in std_logic_vector(width-1 downto 0); in4 : in std_logic; out1, out2 : out std_logic_vector(width-1 downto 0));end diagram;architecture BHV of example is –Region 1: Write code below initializing any signals here–begin process(clk, rst) begin — Region 2: Write code — elsif (rising_edge(clk)) then — Region 3: Write Code — end if; end process;– Region 4: Write Code –end BHV;