Assume you have a pipelined datapath for the following loop….
Assume you have a pipelined datapath for the following loop. Assume separate input and output memories, each with bandwidths of 256 bits per cycle. Assume you are using an FPGA with 32 multipliers. How many iterations of the loop can be performed in parallel? Assume an unsigned short is 16 bits. unsigned short a, b;for (int i=0; i < 1000000; i++) { a = b*10 + b*20 + b*30 + b*40;}