A person is using a rope to lower a 9.5-N bucket into a well with a constant speed of 1.0 m/s. What is the magnitude of the tension force exerted by the rope on the bucket?

A projectile is fired from ground level with a speed of 150 m/s at an angle 30° above the horizontal on an airless planet where g = 10.0 m/s 2. What is the horizontal component of its velocity after 4.0 s?

Vector A → is directed along the positive y-axis and has a magnitude of 3 . 80  units. Vector B → is directed along the negative x-axis and has a magnitude of 1.80 units. What is the magnitude of A → + B → ?

A certain object is being exerted an Fnet = 125 N. As a result, the object accelerates with an acceleration of 24.0 m/s2. The mass of the object is

For each of the following questions, select the option which is most often true:   Increases, decrease, doesn’t affect   Increasing the capacity of a cache                   its access time Decreasing the capacity of a cache                  its miss rate Decreasing the capacity of a cache                    its miss penalty Increasing a cache’s hit rate                       the effective average memory access time Assuming constant capacity, increasing a cache’s block size (cache line size) ________________the amount of tag storage required

Extend a 16-bit signal named “imm” to a 32-bit wire named outimm in one line of code

Rank the following types of memories in terms of average memory access time:      Disk storage, Register, Main Memory, L1 Cache, L2 Cache        Fastest                                                                                                                                      Slowest 

Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses.    3, 180, 43, 2, 191   For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Word Address Binary Address (8 Bits is sufficient) Tag Index Hit/Miss 3         180         43         2         191        

How many clock cycles does it take to execute multMemPow2? Show your answer in the pipelining table below.     Cycle # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 lw                                               beq                                               sll                                               addi                                               sw                                               j                                               beq                                               jr                                              

Examine the function prototype and MIPS implementation below.   // sets *value = (*value) * 2^pow using shifting instructions int multMemPow2(int *value, unsigned int pow);   multMemPow2:   1 lw $v0, 0($a0) # load value 2 loop: beq $a1, $0, exit # exit condition 3 sll $v0, $v0, 1 # multiply by 2 4 addi $a1, $a1, -1 # decrement counter 5 sw $v0, 0($a0) # store result 6 j loop 7 exit: jr $ra   We are using a 5 – stage MIPS pipelined datapath with separate I$ and D$ that can read and write to registers in a single cycle. Assume no other optimizations (no forwarding, no branch prediction, etc.). The default behavior is to stall when necessary. Branch checking is done during the Execute stage.   For parts (1)‐(3), let pow=1. When we ask for clock cycles to execute multMemPow2, we mean from the instruction fetch of lw up to and including the write back of jr.   How many instructions are executed in multMemPow2?