The term ___________________ is a disease, structure, operation, or procedure named for the person who discovered or described it first. 

The medical term that means pounding or racing heart is ____________________.

Accuracy in spelling medical terms is extremely important.

The meaning of the word root cyan/o is _____________.

The meaning of the word root cyan/o is _____________.

Identify is the plural form of ovum _____________________. 

For coding problems write the code to have no compile, simulation, or synthesis errors. Declare all variables. Write your code in Verilog or System Verilog. Write your code with good organization. If you have blocks indent them for full credit. Your answer must be complete and clear. If you use System Verilog clearly state you are using it for credit. Your code should be efficient, succinct (about the minimum number of lines). Do not use compiler directives, and if you don’t know how to do that don’t worry about it. a) Write a half adder module named HA that adds single bit input A and B and places this in output S. The carry out should be named Cout.  Remember that S = A^B, and Cout is true if both A and B are true.   b) Write a positive edge triggered JK flipflop named JKff. You need inputs J, K, and clk, and output Q. Use only these inputs and outputs in your solution. Remember that the JK is like the SR flipflop (J is similar to S, K is similar to R) except that it toggles output Q when J and K are both true. Where J=K=true Q*=Q’ rather than being a don’t care. For full credit, the solution must use a fully simplified Boolean expression for Q. Note there is a SR flipflop table in the cheat sheet which may help. Remember Q is both the output (we call this Q* for Q later in time) and an input (this is the current Q). Hints: The solution should use an always with sensitivity to the positive edge of the clock clk.

Write all code in Verilog or System Verilog so that it would compile, simulate, and synthesize without errors or warnings, for full credit indent blocks and organize your code clearly. All variables must be declared. If you use System Verilog clearly state you are using it for credit. Your code should be efficient, succinct (about the minimum number of lines). Use the Boolean expression from the previous problem. Organize your work and answer carefully. Disorganized solutions and responses will be penalized. a) Write a Verilog or System Verilog module named Funb that evaluates F using a Boolean expression. To get credit this should be done using a Behavioral model in the form of a Boolean expression in Verilog. Use the original, unsimplified of the expression. Inputs are A, B and C. Output is F. b) Is this statement True or false (only one answer) — The structural model causes the synthesizer to build the logic exactly as described, whereas the behavioral model builds the simplest structure that has that behavior. Your answer to b) should be simply True or False.

Bonus (worth less points and graded more critically, because it is a bonus) In this Bonus you will write a testbench named RAtest to test this Ripple adder // 4 bit inputs A, B, and 1 bit input Cin (carry in), // these inputs are added by the ripple adder // output 4 bit Sum of input, 1 bit Cout (carry out) // and overflow OF module RA (input A, B, input Cin, output reg Sum, output Cout, OF); … you don’t have to fill this in and won’t get credit for filling it in if you do endmodule   Write in your testbench in Verilog or System Verilog and add AA = 4’b0110 and BB = 4’b0011 and Cin = 1’b1 using the ripple adder described above. The testbench should have have an initial statement, instantiation, and delays. If you use System Verilog clearly state you are using it for credit. Display all results (Sum, Cout, OF) to the screen using a $display statement (there is an example in the cheat sheet). Write your code with good organization. If you have blocks indent them for full credit. Your answer must be complete, succinct, and clear and with no compile, simulation, or synthesis errors. Also, What should the resulting value of Sum, Cout, and OF in this case be? Is Sum correct?

Write all code in Verilog or System Verilog so that it would compile, simulate, and synthesize without errors or warnings, for full credit indent blocks and organize your code clearly. All variables must be declared. If you use System Verilog clearly state you are using it for credit. Your code should be efficient, succinct (about the minimum number of lines). Use the Boolean expression from the previous problem. Organize your work and answer carefully. Disorganized solutions and responses will be penalized. a) Write a Verilog or System Verilog module named Funb that evaluates F using a Boolean expression. To get credit this should be done using a Behavioral model in the form of a Boolean expression in Verilog. Use the original, unsimplified of the expression. Inputs are A, B and C. Output is F. b) Is this statement True or false (only one answer) — The structural model causes the synthesizer to build the logic exactly as described, whereas the behavioral model builds the simplest structure that has that behavior. Your answer to b) should be simply True or False.