Compare the performance of two cache designs for a byte-addr…
Compare the performance of two cache designs for a byte-addressable memory system. The first cache design is a direct-mapped cache (DM) with four blocks, each block holding one four-byte word. The second cache has the same capacity and block size but is fully associative (FA) with a least-recently-used replacement policy. For the following sequences of memory read accesses to the cache, compare the relative performance of the two caches. Assume that all blocks are invalid initially (cold start) and that each address sequence is repeated a large number of times. Ignore compulsory misses when calculating miss rates. All addresses are given in decimal. Fully associative: allow a given block to go in any cache entry Compulsory miss: This occurs when a process starts, or restarts, or touches new data Least-recently used: Choose the one unused for the longest time word 0 = byte 0 to byte 3, when you load word 0 you load all the bytes inside word 1 = byte 4 to byte 7, when you load word 1 you load all the bytes inside and so on Memory Byte Accesses: 0, 4, 0, 4, (repeats). The Miss Rate is: DM Miss Rate FA Miss Rate (a) 0% 0% (b) 0% 100% (c) 100% 0% (d) 100% 50% (e) 100% 100% Memory Byte Accesses: 0, 4, 8, 12, 16, 0, 4, 8, 12, 16, (repeats) The Miss Rate is: DM Miss Rate FA Miss Rate (a) 20% 0% (b) 40% 0% (c) 20% 20% (d) 40% 100% (e) 100% 100% Memory Byte Accesses: 0, 4, 8, 12, 16, 12, 8, 4, 0, 4, 8, 12, 16, 12, 8, 4, The Miss Rate is: DM Miss Rate FA Miss Rate (a) 25% 0% (b) 25% 25% (c) 50% 0% (d) 50% 100% (e) 100% 100%