Instructions Answer each of the exam problems shown below o…
Instructions Answer each of the exam problems shown below on your printed answer sheet. Write your answers clearly. For problems 2-5, to receive credit or partial credit, you must show your work. Draw a box around your final answer. Problem 1 What is the output characteristic of a MOSFET connected in the common source configuration? A plot of ID vs. VGD A plot of ID vs. VGS A plot of ID vs. VDG A plot of ID vs. VDS A plot of VDS vs. VGS What is the direction of current flow in N- and P-channel MOSFETs? Out of the drain for NMOS and out of the drain for PMOS. Out of the drain for NMOS and into the drain for PMOS. Into the drain for NMOS and into the drain for PMOS. Into the drain for NMOS and out of the drain for PMOS. None of the above Why must the magnitude of an inverter’s voltage gain be greater than 1? To minimize the dynamic power To maximize the speed To provide noise margins To minimize the magnitude of the noise To minimize the static power What aspect of a CMOS inverter’s performance is most strongly controlled by the on current? The speed The dynamic power The static power The noise margins The voltage gain What are the units of the quantity, \(g_m/C_{TOT}\)? Seconds 1/seconds Volts 1/volts Siemens How does the self-gain vary as the channel length, L increases? It increases It decreases It reaches a maximum at the optimum L It reaches unity at the optimum L It is independent of L What is the theoretical minimum subthreshold swing at T = 300 K? 30 mV/decade 60 mV/decade 90 mV/decade 120 mV/decade 150 mV/decade The ON-current for a P-channel MOSFET occurs when the device is biased how? (The power supply voltage is \({V_{DD}}\) .) \({V_{GS}} = {V_T}\), \({V_{DS}} = {V_{DD}}\) \({V_{GS}} = – {V_T},\;{V_{DS}} = – {V_{DD}}\) \({V_{GS}} = {V_{DD}},\;{V_{DS}} = {V_{DD}}\) \({V_{GS}} = – {V_{DD}},\;{V_{DS}} = – {V_{DD}}\) \({V_{GS}} = {V_T},\;{V_{DS}} = 0\) Which of the following describes a P-channel MOSFET operating above threshold? \({V_{GS}} > {V_T}\) \({V_{GS}} < {V_T}\) \({V_{DS}} > {V_T}\) \({V_{DS}} < {V_T}\) \({V_{DS}} > {V_{DSAT}}\) Which of the following is true? Compact physics models succinctly describe the essential physics of a device. Compact circuit models are used by designers – to design circuits and to communicate with manufacturing. The core of a compact circuit model should be a compact physics model. Compact circuit models must satisfy the needs of designers as well as the mathematical constraints of the circuit simulator. All of the above Problem 2 The IV characteristics below are for a 32 nm P-MOSFET. Assume W = 1 micrometer, that the gate capacitance in strong inversion is \({C_{ox}} = 2.6\;{\rm{\mu F/c}}{{\rm{m}}^{\rm{2}}}\) and the series resistance at the source is \({R_S} = 80\;\Omega \). What is the approximate transconductance when the device is biased at maximum drain current? Read numbers from the plot as accurately as possible and clearly explain how you arrived at your answer. Be sure to include units. What is the off-current of this transistor? Be sure to include units. Problem 3 The IV characteristics below for the same 32 nm P-MOSFET as in problem 2). Assume W = 1 micrometer, that the gate capacitance in strong inversion is \({C_{inv}} = 2.6\;\mu {\rm{F/c}}{{\rm{m}}^{\rm{2}}}\) and the series resistance at the source is \({R_S} = 80\;\Omega \). What is the approximate threshold voltage of this MOSFET? What is the approximate number of holes per \(cm^2\) at the virtual source under on-current conditions? Problem 4 For \({V_{GS}} > {V_T}\), a MOSFET is described by: \(I_D = 1.0 mA\) \({V_{DS}} < {V_{GS}} - {V_T}\) \(I_D = 0.5(V_{GS} - 0.2)^2 (1+ 0.1V_{DS}) mA\) \({V_{DS}} \ge {V_{GS}} - {V_T}\) What is the small signal transconductance at \({V_{GS}} = {V_{DS}} = 1.0\) V? Be sure to include units. What is the small signal output resistance at \({V_{GS}} = {V_{DS}} = 1.0\) V? What is the self-gain of this transistor? Problem 5 A CMOS inverter is shown below. Assume that \({V_{DD}} = 1.2\) V and that for \({V_{GS}} > {V_T}\), the NMOS transistors is described by \(I_D = 1.0 mA\) \({V_{DS}} < {V_{GS}} - {V_T}\) \(I_D = 0.5(V_{GS} - 0.2)^2 (1+ 0.1V_{DS}) mA\) \({V_{DS}} \ge {V_{GS}} - {V_T}\) Assume that the P-MOS transistor is a mirror image of the N-MOS transistor. What are the equations that describe this P-MOS transistor? Assume that \({V_{IN}} = 0.6\) V. In what regions are the two transistors operating in? What drain current flows when \({V_{IN}} = 0.6\) V? Congratulations! You are almost done with this exam. DO NOT end the Honorlock session until you have submitted your work to Gradescope. Submission Instructions Use your phone to scan your answer sheet and save it as a PDF. Make sure your scan is legible! Email the PDF to yourself or save it to the cloud (Google Drive, etc.). Click the following link to submit your work to Gradescope: Link to Gradescope Select Exam 1. Follow the prompts to upload your PDF. Match the problems to your pages. Return to this window, agree to the Honor Statement, and click the Submit Quiz to end the exam and end the Honorlock session.