M.E. Lock The context for this question is the same as the p…
M.E. Lock The context for this question is the same as the previous question. You have designed a bus-based custom non-cache-coherent shared memory DSP (Digital Signal Processor). Each CPU in the DSP has a private cache. The hardware provides the following primitives for the interaction between the private cache of a CPU and the shared memory: fetch(addr): Pulls the latest value from main memory into the cache flush(addr): Pushes the value at addr in the cache to main memory; it does not evict it from the cache hold(addr): Locks the memory bus for addr; no other core can fetch or flush this address until released unhold(addr): Releases the lock on addr You got this generic implementation for a ticket lock algorithm and tried it on your architecture. It did not work. struct ticket_lock { int next_ticket; // The next ticket number to give out int now_serving; // The ticket number currently allowed to enter}; void lock(struct ticket_lock *l) { // Acquire ticket int my_ticket = l->next_ticket++; // Wait for turn while (l->now_serving != my_ticket) { // Spin }} void unlock(struct ticket_lock *l) { l->now_serving++; // Release} b) Identify any one potential flaw in the unlock function when implemented on your architecture.