Referring to the circuit below, the aggressor line is capaci…
Referring to the circuit below, the aggressor line is capacitively coupled to the victim line via a coupling capacitor Cc. The aggressor waveform is shown on the figure On the victim side, a NAND gate drives the line. First input is at logic 1, but the rising transition at the 2nd input cause a slow falling waveform on the victim line as shown. Assume this waveform shown on the victim line is before the coupling event. What type of crosstalk event is expected to occur at the input of the OR gate (marked with a question mark) due to this coupling? victimline_UPSCALED-upscaled.jpg