The critical path of a given circuit has cell delays of 0.9…
The critical path of a given circuit has cell delays of 0.9 ns, interconnect delays of 2.1 ns, and a clock skew of 1.1. For a setup time of 0.2 ns, what is the setup slack for this path assuming a 5 ns clock period? Give the exact answer in nanoseconds, but omit the “ns”.